[FIRRTL] FIRRTLExporter name collides when operations having same name attr

[sequencer]

See this mlirblock, it has a valid ssa:

#loc = loc(unknown)
"firrtl.circuit"() <{annotations = [], name = "NoName"}> ({
  "firrtl.module"() <{annotations = [], layers = [], portAnnotations = [], portDirections = array<i1: false, true>, portLocations = [#loc, #loc], portNames = ["i", "o"], portSymbols = [], portTypes = [!firrtl.uint<32>, !firrtl.uint<32>], sym_name = "NoName"}> ({
  ^bb0(%arg0: !firrtl.uint<32>, %arg1: !firrtl.uint<32>):
    %0 = "firrtl.wire"() <{name = "io", nameKind = #firrtl<name_kind droppable_name>}> : () -> !firrtl.bundle<i flip: uint<32>, o: uint<32>>
    %1 = "firrtl.subfield"(%0) <{fieldIndex = 0 : ui32}> : (!firrtl.bundle<i flip: uint<32>, o: uint<32>>) -> !firrtl.uint<32>
    "firrtl.connect"(%1, %arg0) : (!firrtl.uint<32>, !firrtl.uint<32>) -> ()
    %2 = "firrtl.subfield"(%0) <{fieldIndex = 1 : ui32}> : (!firrtl.bundle<i flip: uint<32>, o: uint<32>>) -> !firrtl.uint<32>
    "firrtl.connect"(%arg1, %2) : (!firrtl.uint<32>, !firrtl.uint<32>) -> ()
    %3 = "firrtl.subfield"(%0) <{fieldIndex = 1 : ui32}> : (!firrtl.bundle<i flip: uint<32>, o: uint<32>>) -> !firrtl.uint<32>
    %4 = "firrtl.subfield"(%0) <{fieldIndex = 0 : ui32}> : (!firrtl.bundle<i flip: uint<32>, o: uint<32>>) -> !firrtl.uint<32>
    %5 = "firrtl.subfield"(%0) <{fieldIndex = 0 : ui32}> : (!firrtl.bundle<i flip: uint<32>, o: uint<32>>) -> !firrtl.uint<32>
    %6 = "firrtl.add"(%4, %5) : (!firrtl.uint<32>, !firrtl.uint<32>) -> !firrtl.uint<33>
    %7 = "firrtl.node"(%6) <{name = "tests", nameKind = #firrtl<name_kind interesting_name>}> : (!firrtl.uint<33>) -> !firrtl.uint<33>
    "firrtl.connect"(%3, %7) : (!firrtl.uint<32>, !firrtl.uint<33>) -> ()
    %8 = "firrtl.subfield"(%0) <{fieldIndex = 1 : ui32}> : (!firrtl.bundle<i flip: uint<32>, o: uint<32>>) -> !firrtl.uint<32>
    %9 = "firrtl.subfield"(%0) <{fieldIndex = 0 : ui32}> : (!firrtl.bundle<i flip: uint<32>, o: uint<32>>) -> !firrtl.uint<32>
    %10 = "firrtl.subfield"(%0) <{fieldIndex = 0 : ui32}> : (!firrtl.bundle<i flip: uint<32>, o: uint<32>>) -> !firrtl.uint<32>
    %11 = "firrtl.add"(%9, %10) : (!firrtl.uint<32>, !firrtl.uint<32>) -> !firrtl.uint<33>
    %12 = "firrtl.node"(%11) <{name = "tests", nameKind = #firrtl<name_kind interesting_name>}> : (!firrtl.uint<33>) -> !firrtl.uint<33>
    "firrtl.connect"(%8, %12) : (!firrtl.uint<32>, !firrtl.uint<33>) -> ()
  }) : () -> ()
}) : () -> ()

When export firrtl:

circuit NoName :
  public module NoName :
    input i : UInt<32>
    output o : UInt<32>

    wire io : { flip i : UInt<32>, o : UInt<32> }
    connect io.i, i
    connect o, io.o
    node tests = add(io.i, io.i) @[/home/sequencer/projects/zaozi/zaozinew/tests/src/Smoke.scala 16]
    connect io.o, tests @[/home/sequencer/projects/zaozi/zaozinew/tests/src/Smoke.scala 16]
    node tests = add(io.i, io.i) @[/home/sequencer/projects/zaozi/zaozinew/tests/src/Smoke.scala 16]
    connect io.o, tests @[/home/sequencer/projects/zaozi/zaozinew/tests/src/Smoke.scala 16]

Since the attribute names of %7 and %12 are same, node name will collide.

The X-Problem is: in the eDSL designing, managing namespace is not a useful anymore when it can directly refer to the SSA via C-API, I removed the namespace management in zaozi and hit this bug.