Here you can find documentation on the internal architecture of BSC and other helpful information for people who want to contribute to the source code.
Feel free to ask questions on GitHub (in an Issue or a Discussion)
or on the bsc-dev mailing list.
The bsc-dev list is for questions that are only relevant to developers,
to keep traffic on the b-lang-discuss
mailing list light for people who are just users.
At the moment there is no formal documentation. However, there are written responses to questions on GitHub and the mailing lists, that can someday be collected and turned into a document. The following is a running list of those writings.
- BSC is a series of stages
- This write-up includes a link to the following (incomplete) diagrams of the BSC stages
- See also this brief breakdown of BSC by its three internal representations (CSyntax, ISyntax, ASyntax)
- Briefly on printing and dumping from BSC and intermediate files
- More on the stages, the backend split, Bluesim stages, and the structure of Bluesim output
- The meaning of
.boand.bafiles and compiler flow - Hidden flags
- BSC has a flag
-help-hiddenfor developers, which shows more information than the-helpfor users - Like the LaTeX documentation for flags in the BSC User Guide,
there is short LaTeX document for hidden flags at BS Inc (called
internal-user-guide), which could become part of a BSC Developer Guide
- BSC has a flag
- See INSTALL.md for info on building and installing
- TBD: Any info on tools, dependencies, and compiling options
- e.g. individual SMT libraries can be omitted using
STP_STUB=1orYICES_STUB=1
- e.g. individual SMT libraries can be omitted using
- See the test suite's own README file
- See the link on the use of SMT solvers, below
- How to add a new evaluator primitive to BSC
- specifically how to add a function to get the current module name
- See the link on the use of SMT solvers, below
- Understanding scheduling
- See the link on the use of SMT solvers, below
- Naming conventions in the generated Verilog
- Verilog/Bluesim "main" and the naming of clock and reset ports
- BSC's deduction of portprops
- How to use the different Verilog directories (for different synth tools)
- See the link on Bluesim stages, above, under Basics
- How Bluesim works (mostly the VCD dumping)
- How Bluesim provides implementations for import-BVI
- How the Bluesim C API is imported into Bluetcl
- There is a template for making Bluesim standalone programs (without Tcl) in
bsc/util/bsim_standalone/
- Support for reflection in BSC
- specifically, Bluetcl (outside the language) and Generics (inside the language)
- See the link on how Bluesim's C API is imported into Bluetcl, above, under Bluesim
- The ways that SMT solvers are used in BSC
- SAT solver usage and dumping
- TBD: Status of the SMT solver source codes and how they are incorporated into BSC
- Clock/reset inference
- BSC implements certain design decisions for clocks and resets --
for example, the choice to implement reset inside of state elements (to ignore the
ENinput) instead of outside (as part of theRDYlogic) -- and there may be some documentation (perhaps internal to BS Inc) on those decisions- There was a paper at MEMOCODE 2006,
"Reliable Design with Multiple Clock Domains"
- An earlier version of this paper was submitted to DCC'06 (Designing Correct Circuits)
- There is a BS Inc document from 16 Dec 2004 (
mcd.pdf) that discusses some options, but only clocks, not yet reset - There is a BS Inc document from 28 Oct 2004 (
resets.txt) that purports to be "a proposal on reset handling" but is very prelimary about the problem, not yet the solution - There is a BS Inc file
bsc-doc/doc/MCD-extensions.txtthat describes the new things in BSC to support MCD, both user visible attributes and the BSC source code changes - The BS Inc training slides include a lecture on MCD
- There was a paper at MEMOCODE 2006,
"Reliable Design with Multiple Clock Domains"